//Stephen Kirksharian
//Robert Harkreader
//CPSC 321
//DUE 4/27/08

//Initialize all the registers
module regFile(readreg1, readreg2, writereg, writedata, clk,regwriter, Reset_L, A, B);
 parameter Reg_size = 31, Reg_number = 31; //31=32 since starts at 0
 parameter Reg_add_size = 4; //Register address size is 5 bit to hold one of the
                             //32 values

 output [Reg_size:0] A, B;
 reg  [Reg_size:0] A, B; 
 input  [Reg_size:0] writedata;
 input  [Reg_add_size:0]  readreg1, readreg2, writereg;
 input  clk, Reset_L,regwriter;

 //The 32 registers
 reg    [Reg_size:0] register[0:Reg_number];
 
 integer i;
 

  always @(negedge clk)
  begin
    assign A = register[readreg1];
    assign B = register[readreg2];
  end 

always @(negedge clk)
  begin
    if(~Reset_L) //if reset since negative logic.
    begin 
       //test numbers !!
        register[0] = 0;
	register[1] = 0;
	register[2] = 0;
	register[3] = 0;
	register[4] = 0;
	register[5] = 0; 
	register[6] = 0;
	register[7] = 0;
	register[8] = 0;
	register[9] = 0;
	register[10] = 0;
	register[11] = 0;
	register[12] = 0;
	register[13] = 0;
	register[14] = 0;
	register[15] = 0;
	register[16] = 0;
	register[17] = 0;
	register[18] = 0;
	register[19] = 0;
	register[20] = 0;
	register[21] = 0; 
	register[22] = 0;
	register[23] = 0;
	register[24] = 0;
	register[25] = 0;
	register[26] = 0;
	register[27] = 0;
	register[28] = 0;
	register[29] = 0;
	register[30] = 0;
	register[31] = 0;
       //what we really want it to do
     /* for(i=0; i<Reg_number; i = i+1)
         register[i] <= 0; */
    end
    if(regwriter&&Reset_L)
    begin
	if(writereg!=0) begin
      		register[writereg] <= writedata;
	end
    end
  end

endmodule
